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Evaluation Board User Guide
193X_MCLKI
DISABLE
193X_MCLKI
DISABLE
UG-040
JP18
JP20 MCLKO C147
JP18
JP20 MCLKO C147
L7
JP19
1938_MCLKI
R160 JP22
XTAL
U18
J22
L7
JP19
1938_MCLKI
R160 JP22
XTAL
U18
J22
C158
JP23
CPLD
U21
Y1
R167
193X_MCLKO
C158
JP23
CPLD
U21
Y1
R167
193X_MCLKO
JP25
JP25
OSC DISABLE HDR1
OSC DISABLE HDR1
HDR2
JP27
JP28
EXT CLK
JP29
R174
R169
R172
U22
R175
J23
HDR2
JP27
JP28
EXT CLK
JP29
R174
R169
R172
U22
R175
J23
8416
JP30
C168
C170
EXT CLK IN
8416
JP30
C168
C170
EXT CLK IN
HDR2
JP31
HDR1
Figure 10. External Clock In as Master; the AD1939 and CPLD as Slaves
193X_MCLKI
DISABLE
HDR2
JP31
HDR1
Figure 12. Passive Crystal; the AD1939 Is Master and the CPLD Is Slave from
the MCLKO Port
193X_MCLKI
DISABLE
JP18
JP20 MCLKO C147
JP18
JP20 MCLKO C147
L7
JP19
1938_MCLKI
R160 JP22
XTAL
U18
J22
L7
JP19
1938_MCLKI
R160 JP22
XTAL
U18
J22
C158
JP23
CPLD
U21
Y1
R167
193X_MCLKO
C158
JP23
CPLD
U21
Y1
R167
193X_MCLKO
JP25
JP25
OSC DISABLE HDR1
OSC DISABLE HDR1
HDR2
JP27
JP28
EXT CLK
JP29
R174
R169
R172
U22
R175
J23
HDR2
JP27
JP28
EXT CLK
JP29
R174
R169
R172
U22
R175
J23
8416
JP30
C168
C170
EXT CLK IN
8416
JP30
C168
C170
EXT CLK IN
HDR2
JP31
HDR1
Figure 11. Active On-Board Oscillator as Master; the AD1939 and
CPLD as Slaves
The MCLK configurations shown in Figure 12 and Figure 13
use the AD1937/AD1939 MCLKO port to drive the CPLD and,
possibly, the HDRs. The passive crystal runs the AD1937/AD1939
at 12.288 MHz. Figure 13 shows the MCLKI shut off; this is the
case when the PLL is set to lock to LRCLK instead of to MCLK.
HDR2
JP31
HDR1
Figure 13. LRCLK Is the Master Clock Using the PLL; MCLKI Is Disabled, and
CPLD Is Slave to the MCLKO Port
CONFIGURING THE PLL FILTER
The PLL for the AD1937/AD1939 can run from either MCLK
or LRCLK, according to its setting in the PLL and Clock Control 0
register, Bits[6:5]. The matching RC loop filter must be con-
nected to LF (Pin 61) using JP15. See Figure 14 and Figure 15
for the jumper positions.
Rev. 0 | Page 5 of 32
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